/*
## code 
           
 <details> 
           
```verilog
*/
// *******************************************************************************
//!Company: Fpga Publish
//!
//!Engineer: FP 
//!
// 
// Create Date: 2024/03/24 23:00:28
// Design Name: 
// Module Name: led_line_driv
// Project Name: 
// Target Devices: ZYNQ7010 | XCZU2CG | Kintex7
// Tool Versions: 2021.1 || 2022.2
// Description: 
//         * 
// Dependencies: 
//         * 
//!-----------------
//!Revision: 0.01 
//!
//!Revision 0.01 - File Created
//!
//!Revision 0.02 - add default mode set
//!

//Additional Comments:
// 
// *******************************************************************************
`timescale 1ns / 1ps

module led_line_driv #(
    //led 
    parameter WD_LED = 8, //! led line width 
    //light mode 
    parameter WD_DELAY_CNT = 27,//! control light fre
    parameter MD_DEFAULT_INV = 0,//! invert light mode,default is 1, and invert is 0 
    //sim mode
    parameter MD_SIM_ABLE = 0,//!mode in sim mode enable
    //error info
    parameter WD_ERR_INFO = 4 //!width of error info
   )(
    //system signals
    input           i_sys_clk   , //!in system clock 
    input           i_sys_resetn, //!in system reset_n 
    //! trig signal
    input  [WD_LED-1:0] i_trig_led_light, //trig for led light
    //! @virtualbus led @dir out --
    output [WD_LED-1:0] o_port_led_line, //! led line light
    //! @end 
    //  -----------------------------------
    //error info feedback
    //![0]:
    //![1]:
    output   [WD_ERR_INFO-1:0]  m_err_led_info1 //!master of error info
);
//========================================================
//function to math and logic

//========================================================
//localparam to converation and calculate

//========================================================
//register and wire to time sequence and combine
// ----------------------------------------------------------
//! delay count
reg [WD_DELAY_CNT-1:0] r_delay_cnt_fifo [0:WD_LED-1]; //led delay cnt fifo
//========================================================
//always and assign to drive logic and connect
generate genvar i;
    for(i = 0; i < WD_LED; i = i + 1)
    begin:FOR_WD_LED
        always@(posedge i_sys_clk)
        begin
            if(!i_sys_resetn) //system reset
            begin
                r_delay_cnt_fifo[i] <= 1'b0; //
            end
            else if(!r_delay_cnt_fifo[i][WD_DELAY_CNT-1]) //still cnt until full
            begin
                r_delay_cnt_fifo[i] <= r_delay_cnt_fifo[i] + 1'b1;
            end
            else if(i_trig_led_light[i]) //
            begin
                r_delay_cnt_fifo[i] <= 1'b0;  //
            end
            
        end
        assign o_port_led_line[i] = MD_DEFAULT_INV ? ~r_delay_cnt_fifo[i][WD_DELAY_CNT-2] : r_delay_cnt_fifo[i][WD_DELAY_CNT-2]; //make led light flash when monitor trig
    end
endgenerate

//========================================================
//module and task to build part of system

//========================================================
//expand and plug-in part with version 

//========================================================
//ila and vio to debug and monitor


endmodule
              
/* end verilog
```           
              
 </details>   
## logic      
              
## sim        
              
*/            